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Realtek Mini Pci-e WLAN Card RTL8187B
- 128-Pin LQFP with ‘Green?package
- State machine implementation without external memory (RAM, flash) requirement
- Complies with IEEE 802.11 b/g standards
- Supports descriptor-based buffer management
- Integrated Wireless LAN MAC and Direct Sequence Spread Spectrum/OFDM Baseband Processor in one chip
- Enhanced signal detector, adaptive frequency domain equalizer, and soft-decision Viterbi decoder to alleviate severe multipath effects
- Processing Gain compliant with FCC
- On-Chip A/D and D/A converters for I/Q Data, AGC, and Adaptive Power Control
- Supports both transmit and receive Antenna Diversity
- Data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36, 48, and 54Mbps
- Supports 40MHz OSC as the internal clock source. The frequency deviation of the OSC must be within 25 PPM on IEEE 802.11g
- IEEE 802.11g protection mechanisms for both RTS/CTS and CTS-to-self
- Burst-mode support for dramatically enhanced throughput
- DSSS with DBPSK and DQPSK, CCK modulations and demodulations supported with long and short preamble
- OFDM with BPSK, QPSK, 16QAM and 64QAM modulations and demodulations supported with rate compatible punctured convolutional coding with coding rate of 1/2, 2/3, and 3/4
- Efficient IQ-imbalance calibration, DC offset, phase noise, frequency offset and timing offset compensation reduce analog front-end impairments
- Selectable digital transmit and receiver FIR filters provided to meet transmit spectrum mask requirements and to reject adjacent channel interference
- Programmable scaling both in transmitter and receiver to trade quantization noise against the increased probability of clipping
- Fast receiver Automatic Gain Control (AGC) & antenna diversity functions
- Complies with WMM, 802.11e, and CCX specifications
- Complies with 802.11h, 802.11i, 802.11j specifications
- Hardware-based IEEE 802.11i encryption/decryption engine, including 64-bit/128-bit WEP, TKIP, and AES
- Supports Wi-Fi alliance WPA and WPA2 security
- Contains two large independent transmit and receive FIFO buffers
- Advanced power saving mode when the LAN and wakeup function are not used
- Uses 93C46 (64*16-bit EEPROM) or 93C56 (128*16-bit EEPROM) to store resource configuration and ID parameter data
- LED pins for various network activity indications
- Six GPIO pins supported
- Supports digital loopback capability on both ports
- Scatter and gather operation
- Complies with USB Specification 2.0
- Supports Full-speed (12Mbps) and High-speed (480Mbps)
- Embedded standard 8051 CPU with enhanced features:
- Four cycles per instruction
- Variable clock speed cuts power consumption
- Supports 9 endpoints:
- 64-Byte buffer for control endpoint
- Two 512-Byte buffers for bulk IN endpoint
- Seven 512-Byte buffers for bulk OUT endpoint
- 3.3V and 1.5V power supplies required
- 5V tolerant I/Os
- 0.15μm CMOS process
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