RealTek RTL8187 RTL8187se Half Mini 802.11 b/g PCIe Wireless WiFi WLAN Card PCI-Express

Realtek Mini Pci-e WLAN Card RTL8187se

• 64-Pin QFN with ‘Green’ package
• State machine implementation without external memory (RAM, flash) requirement
• Complies with IEEE 802.11b/g standards
• Supports descriptor-based buffer management
• Integrated Wireless LAN MAC and Direct Sequence Spread Spectrum/OFDM Baseband Processor in one chip
• Enhanced signal detector, adaptive frequency domain equalizer, and soft-decision Viterbi decoder to alleviate severe multipath effects
• Processing Gain compliant with FCC
• On-Chip A/D and D/A converters for I/Q Data, AGC, and Adaptive Power Control
• Supports both transmit and receive Antenna Diversity
• Data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36, 48, and 54Mbps
• Supports 40MHz OSC as the internal clock source. The frequency deviation of the OSC must be within 25ppm on IEEE 802.11g
• PCI Express bus controller
  • Complies with PCI Express 1.1 and PCI Express Mini Card Electromechanical Specification Revision 1.1
  • PCI power management Revision 1.2
  • Supports PCI  Express Active State Power Management (ASPM)
  • Provides PCI Express bus data transfers and PCI Express memory space or IO space mapped data transfers of the RTL8187SE’s operational registers
  • Supports ACPI (Rev 1.0, 1.0b, 2.0)
• Supports Wake-On-WLAN (WoWLAN) function and remote wake-up (Magic Packet and Microsoft® wake-up frame)
• Supports auxiliary power auto-detect, and sets the related capability of power management registers in PCI Express configuration space
• IEEE 802.11g protection mechanisms for both RTS/CTS and CTS-to-self
• Burst-mode support for dramatically enhanced throughput
• DSSS with DBPSK and DQPSK, CCK modulations and demodulations supported with long and short preamble
• OFDM with BPSK, QPSK, 16QAM and 64QAM modulations and demodulations supported with rate compatible punctured convolutional coding with coding rate of 1/2, 2/3, and 3/4
• Efficient IQ-imbalance calibration, DC offset, phase noise, frequency offset and timing offset compensation reduce analog front-end impairments
• Selectable digital transmit and receiver FIR filters provided to meet transmit spectrum mask requirements and to reject adjacent channel interference
• Programmable scaling both in transmitter and receiver to trade quantization noise against the increased probability of clipping
• Fast receiver Automatic Gain Control (AGC) & antenna diversity functions
• Adaptive transmit power control function
• Complies with WMM, 802.11e, and CCX specifications
• Complies with 802.11i and 802.11j specifications
• Hardware-based IEEE 802.11i encryption/decryption engine, including 64-bit/128-bit WEP, TKIP, and AES
• Supports Wi-Fi alliance WPA and WPA2 security
• Supports a 32-bit general-purpose timer
• Contains two large independent transmit and receive FIFO buffers
• Advanced power saving mode when the LAN and wakeup function are not used
• Uses 93C46 (64*16-bit EEPROM) or 93C56 (128*16-bit EEPROM) to store resource configuration and ID parameter data
• LED pins for various network activity indications
• Nine GPIO pins supported
• Supports digital loopback capability on both ports
• Flexible RF transceiver interface for different RF transceiver applications
• Built-in 3.3V to 1.8V regulator
• 3.3V power supply required
• 0.18μm CMOS process